LimeSDR FPGA Gateware
  • Introduction
  • Project Structure
    • Overview
    • Root Directory
    • Directory Details
      • boards/
      • doc/
      • firmware/
      • gateware/
      • software/
    • File Details
      • riscv_jtag_tunneled.tcl
      • README.rst
      • .gitignore
  • Gateware Description
    • LimeSDR XTRX
      • Main block diagram
      • Soft core CPU module
      • Lime_top module
      • Pcie_phy module
      • I2C0, I2C1 modules
      • Lms_spi module
      • Flash module
  • Building the project
    • Requirements
    • Cloning the Repository
    • Building and loading the Gateware
    • Building/loading VexRiscv firmware trough UART
  • Modifying the project
    • Gateware
      • Example
    • Firmware
    • Debug tools
LimeSDR FPGA Gateware
  • Search

© Copyright 2024, Lime Microsystems Ltd. Last updated on Dec 10, 2024.