LimeSDR FPGA Gateware (LimeSDR_GW) Logo
  • Introduction
  • Project Structure
    • Overview
    • Repository Layout
    • Key Highlights
    • Additional Files
  • Gateware Description
    • LimeSDR XTRX
      • Main Block Diagram
      • Soft core CPU Module
      • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
      • PCIe PHY Module
      • I2C Modules
      • LMS SPI Module
      • Flash Module
    • LimeSDR Mini V1
      • Main Block Diagram
      • Soft core CPU Module
      • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
      • FT601 PHY Module
      • I2C Module
      • Lms_spi Module
      • Flash Module
    • LimeSDR Mini V2
      • Main Block Diagram
      • Soft core CPU Module
      • Lime_top Module
        • LMS7002 Top Module
        • RX Path Top Module
        • TX Path Top Module
      • FT601 PHY Module
      • I2C Module
      • Lms_spi Module
      • Flash Module
  • Building the Project
    • Requirements
    • Cloning the Repository
    • Build/Load/Flash Instructions
      • LimeSDR XTRX
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
      • LimeSDR Mini V1
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
      • LimeSDR Mini V2
        • Available build options
        • User/Golden Bitstreams
        • Programming cables
        • Flashing Instructions
  • Modifying the Project
    • Gateware
    • Firmware
    • Firmware Loading via UART
    • Debug Tools
LimeSDR FPGA Gateware (LimeSDR_GW)
  • Search

© Copyright 2024-2025, Lime Microsystems Ltd. Last updated on May 26, 2025.