LimeSDR Mini V2

This section provides detailed information about the gateware implemented for the LimeSDR Mini V2 board.

Main Block Diagram

The top-level file integrates the following main blocks:

Soft core CPU Module – VexRiscv CPU instance.
Lime_top Module – Wrapper for blocks handling LMS7002M transceiver control and data transfer.
FT601 PHY Module – Handles control and data stream endpoints between CPU, streaming interface, and FT601 device.
I2C Module and Lms_spi Module – Communication interfaces for controlling onboard peripherals.
Flash Module – Module for accessing the FPGA configuration FLASH memory.

Soft core CPU Module

The CPU module is a vexriscv core provided by LiteX. It is specified via the cpu_type parameter for the SoCCore class, which serves as the parent class for the top-level gateware design.

The source code for the CPU can be found at: LiteX VexRiscv core

Lime_top Module

The Lime_top Module serves as a wrapper for the LMS7002M transceiver control and data transfer blocks. Its main sub-blocks include:

LMS7002 Top Module – Implements the LMS7002M PHY for digital IQ sample transmission and reception.
RX Path Top Module – Manages the receive path from the LMS7002M to the FPGA and host, packing IQ samples into packets and generating timestamps.
TX Path Top Module – Manages the transmit path from the host through the FPGA to the LMS7002M, unpacking IQ sample packets and handling stream synchronization with timestamps.

LMS7002 Top Module

This module is part of LimeDFB and more details can be found in lms7002_top description. This module implements the LMS7002M PHY for transmitting and receiving digital IQ samples.

RX Path Top Module

This module is part of LimeDFB and more details can be found in rx_path_top description. It handles the receive path from the LMS7002M to the FPGA and host, including IQ sample packetization and timestamp generation.

TX Path Top Module

This module is part of LimeDFB and more details can be found in tx_path_top description. This module manages the transmit path from the host through the FPGA to the LMS7002M, including unpacking of IQ samples and stream synchronization.

FT601 PHY Module

The FT601 PHY module serves as a wrapper for both the logical and physical interfaces of the FT601 device. It provides the following endpoints and FIFOs:

Control (PC → FPGA): Handles configuration commands from the PC to the FPGA.
Control (FPGA → PC): Enables register readback and status reporting from the FPGA to the PC.
TX Data Path (PC → LMS7002M): Transfers transmission data from the PC to the LMS7002M.
RX Data Path (LMS7002M → PC): Transfers received data from the LMS7002M to the PC.

I2C Module

The I2C0 module is an instance of the I2CMaster class provided by LiteX. It is used for controlling onboard peripherals via the I2C protocol.

The source code can be found here: I2CMaster in LiteX

Lms_spi Module

The Lms_spi Module is an instantiation of the SPIMaster class from LiteX. It handles SPI communication with the LMS7002M transceiver.

Source code: SPIMaster in LiteX

Flash Module

The Flash Module is implemented using the S7SPIFlash class provided by LiteX. It enables access to the FPGA configuration FLASH memory.

Source code: S7SPIFlash in LiteX