LimeSDR XTRX

This section provides information about LimeSDR XTRX gateware

Main block diagram

Top level file contains these main blocks:

  • Soft core CPU - VexRiscv CPU instance

  • Lime_top - blocks specific to lms7002m transceiver control and data transfer

  • Pcie_phy - PCIe block with physical interface and DMA

  • I2C0, I2C1, Lms_spi - communication interfaces to control onboard periphery

  • Flash - FPGA configuration FLASH memory access

../_images/main_block_diagram.svg

Soft core CPU module

CPU module is a vexriscv_smp core provided by LiteX. It is implemented as a cpu_type parameter for the SoCCore class, which is the parent class for the top level of the gateware design.

The source code for the cpu can be found using this link.

Lime_top module

Block lime_top is a wrapper file for specific lms7002m transceiver control and data transfer blocks. Main blocks are following:

  • lms7002_top - lms7002 IC phy for sending/receiving digital IQ samples.

  • rx_path_top - receive path (LMS7002M -> FPGA -> HOST), responsible for packing IQ samples into packets and timestamp generation.

  • tx_path_top - transmit path (HOST -> FPGA -> LMS7002M), responsible for unpacking received packets into IQ samples and stream synchronization with timestamp.

../_images/limetop_block_diagram.svg

Pcie_phy module

Pcie_phy is an instance of S7PCIEPHY class, which is part of LitePCIe. Source code for LitePCIe can be found using this link.

I2C0, I2C1 modules

I2C0 and I2C1 modules are instances of I2CMaster class provided by LiteX. Source code for the class can be found using this link.

Lms_spi module

Lms_spi module is an instance of SPIMaster class provided by LiteX. Source code for the class can be found using this link.

Flash module

Flash module is an instance of S7SPIFlash class provided by LiteX. Source code for the class can be found using this link.