Building the Project
This section explains how to build the gateware and work with the firmware for the supported boards. The build process relies on several mandatory tools (LiteX, SBT, and GHDL) as well as board-specific FPGA toolchains.
Requirements
Before building the project, you must install the following tools:
LiteX Follow the official installation instructions in the LiteX repository.
SBT (Scala Build Tool) Installation instructions can be found here.
GHDL GHDL is required for VHDL-to-Verilog conversion in some targets. See the GHDL repository for installation instructions.
openFPGALoader Universal utility for programming FPGAs. See the openFPGALoader repository for installation instructions.
Additionally, the required FPGA toolchain depends on the target board:
- For LimeSDR XTRX:
Vivado 2022.1 (or later) is required. Download it and install from Xilinx. Free version can be used.
Ensure Vivado’s settings are sourced or its binaries are in your
$PATHbefore building.
- For LimeSDR Mini V1:
Quartus 23.1 (or later) is required. Download it and install from Intel. Free version can be used.
Consult respective toolchain’s documentation for installation details.
Note
While other tool versions might work, it is recommended to use the specified toolchain versions to avoid potential compatibility issues.
Cloning the Repository
To clone the repository and initialize its submodules, run:
git clone https://github.com/myriadrf/LimeSDR_GW.git
git submodule init
git submodule update
Build/Load/Flash Instructions
Gateware for wanted target can be build with folowing command:
python3 -m boards.targets.<target> --build
Note
Ensure required toolchain is installed and configured before building. See Requirements section for respective board.
Make sure to run build command from project root directory.
Detailed build/load/flash instructions and available options for each board can be found below: