LimeSDR FPGA Gateware (LimeSDR_GW)
Introduction
Project Structure
Overview
LimeSDR_GW Repository Layout
LimeDFB Repository Layout
Integration Between Repos
Additional Files
Gateware Description
PCIe and USB Interfacing
Overview of Interface Options
USB Interface (FT601)
PCIe Interface (LitePCIe)
Testing and Debugging Interfaces
Toolchains
FPGA Synthesis Toolchains
RISC-V Firmware Toolchains
Gateware Update Mechanism
Overview
Update Process
Multiboot Across FPGAs
Testing and Recovery
Building the Project
Requirements
Cloning the Repository
Build/Load/Flash Instructions
LimeSDR XTRX
Available build options
User/Golden Bitstreams
Programming cables
Flashing Instructions
LimeSDR Mini V1
Available build options
User/Golden Bitstreams
Programming cables
Flashing Instructions
LimeSDR Mini V2
Available build options
User/Golden Bitstreams
Programming cables
Flashing Instructions
LiteX Basics
Introduction to LiteX in LimeSDR_GW
Overview of LiteX usage in LimeSDR_GW
Benefits of Using LiteX (in the Context of LimeSDR_GW)
Understanding Core LiteX Concepts: Boards, Platforms, Targets
Platform = Board + Constraints
LMS7002M I/O Block on LimeSDR Mini V2
Timing Constraints Generation
Multiple Toolchain Support
Target = SoC Top-Level + Flow Control
How It All Fits Together
Creating LiteX/Migen Wrappers
Example: Wrapping the GPIO Module
General Pattern
Modifying the Project
Gateware
Firmware
Firmware Loading via UART
Debug Tools
Adding a New Board
Tutorial: Developing New LimeDFB Blocks
Tutorial: Adding a Custom Board
Best Practices and Guidelines
Introduction
File, Module, and Signal Naming Conventions
Module and File Structure
Class Naming
Signal Naming
AXIStream Interfaces
CSRs and Registers
Platform Naming and IO Mapping
Recommendations
Developing for Portability Across Devices and Vendors
Unified Platform and IO Abstraction
Cross-Vendor IO Support: Abstracted Primitives
Cross-Vendor PLL and Clocking
Memory Abstraction and Flexibility
Simplified Toolchain Integration
Avoiding Fragmentation of CPU and Firmware
Soft CPU Core Options
Supported CPUs in LiteX
Tested Cores in LimeSDR_GW
Typical Firmware Workloads
Unified Firmware and Tooling
LimeSDR FPGA Gateware (LimeSDR_GW)
Index
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Index