LimeSDR XTRX

This section provides detailed information about the gateware implemented for the LimeSDR XTRX board.

Main Block Diagram

The top-level file integrates the following main blocks:

  • Soft core CPU – VexRiscv CPU instance.

  • Lime_top Module – Wrapper for blocks handling LMS7002M transceiver control and data transfer.

  • PCIe PHY – PCIe block with the physical interface and DMA.

  • I2C0, I2C1 and Lms_spi – Communication interfaces for controlling onboard peripherals.

  • Flash – Module for accessing the FPGA configuration FLASH memory.

Main block diagram for LimeSDR XTRX

Soft core CPU Module

The CPU module is a vexriscv_smp core provided by LiteX. It is specified via the cpu_type parameter for the SoCCore class, which serves as the parent class for the top-level gateware design.

The source code for the CPU can be found at: LiteX VexRiscv SMP core

Lime_top Module

The Lime_top Module serves as a wrapper for the LMS7002M transceiver control and data transfer blocks. Its main sub-blocks include:

  • LMS7002 Top Module – Implements the LMS7002M PHY for digital IQ sample transmission and reception.

  • RX Path Top Module – Manages the receive path from the LMS7002M to the FPGA and host, packing IQ samples into packets and generating timestamps.

  • TX Path Top Module – Manages the transmit path from the host through the FPGA to the LMS7002M, unpacking IQ sample packets and handling stream synchronization with timestamps.

Lime_top block diagram

LMS7002 Top Module

This module is part of LimeDFB and more details can be found in lms7002_top description. This module implements the LMS7002M PHY for transmitting and receiving digital IQ samples.

RX Path Top Module

This module is part of LimeDFB and more details can be found in rx_path_top description. It handles the receive path from the LMS7002M to the FPGA and host, including IQ sample packetization and timestamp generation.

TX Path Top Module

This module is part of LimeDFB and more details can be found in tx_path_top description. This module manages the transmit path from the host through the FPGA to the LMS7002M, including unpacking of IQ samples and stream synchronization.

PCIe PHY Module

The PCIe PHY module is an instantiation of the S7PCIEPHY class from LitePCIe. It provides the physical layer for the PCIe interface, including DMA support.

The source code for LitePCIe is available at: LitePCIe on GitHub

I2C Modules

The I2C0 and I2C1 modules are instances of the I2CMaster class provided by LiteX. They are used for controlling onboard peripherals via the I2C protocol.

The source code can be found here: I2CMaster in LiteX

LMS SPI Module

The Lms_spi module is an instantiation of the SPIMaster class from LiteX. It handles SPI communication with the LMS7002M transceiver.

Source code: SPIMaster in LiteX

Flash Module

The Flash module is implemented using the S7SPIFlash class provided by LiteX. It enables access to the FPGA configuration FLASH memory.

Source code: S7SPIFlash in LiteX